FIELD OF THE INVENTION
This invention relates to a non-volatile semiconductor memory device.
Document 1: A 16 Kb Electrically Erasable Nonvolatile Memory, 1980, IEEEE, ISSCC, Dig. Tech. Pap., pp 152-153, 271, 1980. PA1 Document 2: Analysis and Modeling of Floating-Gate EEPROM Cells, IEEE Trans., Electron Devices, 1986, June, ED-33, No. 6, pp 835-844. PA1 Document 3: Semiconductor MOS Memory and Method of Using the Same, Nikkan Kogyo Newspaper Co., 1990, pp 96-101. PA1 (a) Signals of at least four different voltage values are generated, and one of the signals of at least four different voltage values is selected in accordance with a data signal supplied from the outside and applied to the corresponding memory cell. PA1 (b) Signals of at least four different duration times are generated, and one of the signals of at least four different duration times is selected in accordance with a data signal supplied from the outside and applied to the corresponding memory cell. PA1 (c) Signals of at least four different pulse numbers, are generated and one of the signals of at least four different pulse numbers is selected in accordance with a data signal supplied from the outside and applied to the corresponding memory cell.
A non-volatile semiconductor memory device in which the recorded data is not lost even if the power supply is turned off (hereinafter, referred to as PROM) has already been developed and practically used since the early 1970's. In addition, another non-volatile semiconductor memory device which is electrically erasable (hereinafter, referred to as EEPROM) as described in the document 1 has been practically used since the 1980's. In the write operation of a memory cell of the EEPROM, as described in the documents 1 and 2, the transistor-structure memory cell having a floating gate is charged with electrons and discharged through a thin insulating oxide film by means of the Fowler-Nordheim tunneling phenomenon, so that the threshold voltage of the transistor can be controlled. The threshold value of the memory cell is increased by injecting electrons into the floating gate and decreased by discharging electrons and injecting holes.
FIG. 9 is a circuit block diagram of the conventional EEPROM. In FIG. 9, there are shown 32 memory cells in 4 columns and 8 rows, in which two bits of data are simultaneously read and written for programming. In FIG. 9, there are also shown address input terminals 501, 502, 503 and 504 which are used for inputting the address data for the selected memory cells. Input terminals 505, 506 and 507 are used for inputting control signals for controlling the operation mode of the EEPROM; that is, the input terminal 505 is used for inputting a chip selection signal, the input terminal 506 for inputting an output selection signal, and the input terminal 507 for inputting a write signal. There are shown input/output terminals 508 and 509 from which the stored data of the selected memory cells in the read mode are produced, and to which the data to be stored in the memory cells in the write mode are supplied.
Address buffers 511, 512, 513 and 514 have the function to buffer and output the address data and the function to receive the power-down signal and reduce the consumption current in the input portion.
A chip control circuit 515 is responsive to the control signals at the input terminals 505, 506 and 507 to select the read mode, write mode, power-down mode (or standby mode) and output nonselection mode. The write mode is further divided into two different modes, or an erase mode and a program mode. In the erase mode, the byte or column line of the selected memory cell or memory cells of a memory block are made in the erased state in order for the memory cell or cells to be rewritten with other data to be stored. The erased state of the memory cell means that the threshold value of the memory cell is higher (or lower) than the gate voltage in the read operation. In the program mode, the selected memory cell is made in the programmed state in accordance with the input data. The programmed state means that the threshold value of the memory cell is lower (or higher) than the gate voltage in the read operation. When the memory cell data is rewritten with other data, the erase mode is selected so that the memory cell is made in the erase state, and then made in the programmed state in accordance with the input data. In other words, the write mode includes the erase mode and the program mode. The chip control circuit additionally includes a function to automatically terminate the erase mode and the program mode by means of an internal timer.
A high-voltage generation/control circuit 518 has a circuit for increasing the source voltage supplied to the EEPROM in the write mode to generate a high voltage of about 10 through 25 V (hereinafter, referred to as the charge pump circuit), and a control circuit for supplying a desired high voltage to each circuit of the EEPROM in accordance with the erase mode and program mode. A column decoder 516 decodes the outputs from the address buffers 511 and 512, and applies a high (H) voltage only to the column line (also referred to as the word line) of the selected memory cell, and a low voltage to the column lines of the non-selected cells. A row decoder 517 decodes the outputs from the address buffers 513 and 514, and supplies a high-level signal to the row line of the selected memory cell and a low-level signal to the row lines of the non-selected memory cells through multiplexers 527 and 528. The multiplexers 527 and 528 connect the selected row line (also referred to as the bit line) to data lines 597 and 598 in accordance with the signals from the row decoder. The high level signal from the row decoder 517 is about the source voltage in the read mode and a high voltage in the write mode.
There are shown column lines 529, 530, 531 and 532, and row lines 533, 534, 535, 536, 537, 538, 539 and 540. There are also shown memory sense program lines 577, 578, 579 and 580, and memory cells 545, 546, . . . , 576. The structure and connection of the memory cells are the same as shown in FIGS. 1 and 3 in the document 1.
Data input buffers 520 and 524 buffer the input data from the input/output terminals 508 and 509 and supply the output data to program circuits 519 and 523 in the write mode. The program circuits 519 and 523 receive the signal and high voltage for the program mode, and output the high voltage or low voltage corresponding to the data input to the data lines 597 and 598.
Each of sense circuits 521, 525 detects and amplifies the magnitude of voltage or current values on the data line 597 or 598, to which the data of the memory cell selected in the read mode is transmitted through the row line 533, 534 . . . 540 and a multiplexer 527 or 528, to be outputted to the data output buffer 522, or 526. The data output buffers 522 and 526 supply the data from the sense circuits 521, 525 to the input/output terminals 508, 509 in the read mode. In addition, in the power-down mode and in the output non-selection mode, the data is inhibited from being produced.
Input signal lines 585 through 588 are connected to the multiplexers 527 and 528, respectively, to apply the control signals for switching the multiplexers thereto. The chip control circuit 515 supplies the power-down signal through a signal line 603 to the control input terminals of the address buffers 511, 512, 513 and 514, and supplies a read-enable signal through a signal line 589 to the sense circuits 521 and 525. In the program mode, the chip control circuit also supplies a program signal through a signal line 590 to the program circuits 519 and 523. The high voltage generation/control circuit 518 supplies high-voltage signals to the high-voltage lines 594 and 596, and supplies 0 volt to a memory sense line 595. An erase signal line 591 is connected to the high-voltage generation/control circuit 518, so that in the erase mode, the high-voltage output signal therefrom is supplied to the signal lines 594 and 595. A data input enable signal line 592 is connected to the data input buffers 520 and 524 so that in the write mode the data input buffers can be activated through the signal line. A data output enable signal line 593 is connected to the data output buffers 522 and 526 so that in the read mode the data output buffers can be activated through the signal line.
Circuits 541, 542, 543 and 544 decode the signal on the memory sense line 595 in accordance with the signals on the column lines 529, 530, 531 and 532, producing memory sense program signals 577, 578, 579 and 580, respectively. Shown at 604 is a memory ground line.
The write operation and read operation of the conventional EEPROM will be described briefly. In the read operation, the control signals from the input terminals 505, 506 and 507 are rendered to the read mode, and the selected address data are supplied to the address input terminals 501, 502, 503 and 504. The input address data are buffered by the buffers 511, 512, 513 and 514, and decoded by the column decoder 516 and row decoder 517. A selected one of the four output signal lines of the column decoder 516 is at a high voltage (normally about the source voltage), and the other signal lines are at a low voltage. The switching control signals 585 through 588 from the row decoder 517 are supplied to the multiplexer 527, selecting one of the row lines 533 . . . 536, and the selected row line is electrically connected to the data line 597 through a low impedance.
Similarly, the switching control signals 585 through 588 are supplied to the multiplexer 528, thereby selecting one of the row lines 537 through 540. At this time, a voltage of, for example, 2 through 4 V for detecting the threshold value of the memory cell is supplied on the memory sense line 595, and fed through the circuits 541 through 544 to only the selected one of the memory sense program lines 577, 578 . . . 580. The memory ground line 604 is in the grounded state. The row line of the selected memory cell is supplied with the threshold value detection voltage from the sense circuits 521 and 525. When the threshold voltage of the memory cell is lower than the threshold detection voltage, the selected memory cell transistor is turned on, and thus a current flows from the selected row line to the memory ground line 604. When the threshold voltage of the memory cell is higher than the threshold detection voltage, the selected memory cell transistor is turned off, and thus no current flows from the row line to the memory ground line 604. The voltage on the row line is set by the sense circuit 521 or 525, and the current to the row line in the read mode is supplied from the sense circuit 521 or 525. When this current is detected and amplified by the sense circuit, the stored data in the memory cell is produced in a binary value of a high or low voltage and fed through the data output buffer 522 or 526 to the outside. If the threshold value of the memory cell is as high as 6 V, a high voltage is produced at the input/output terminal 508. If the threshold value of the memory cell is as low as 0 V, a low voltage is produced at the input/output terminal 508.
In the write operation, the data in the memory cell is erased first. The data erasing is normally made for one column line at a time, but may be made for one byte or block. The erase mode is effected by the control input to the input terminals 505, 506, 507. In the erase mode, the column line of the memory cell is selected by the address data from the address input terminals 501, 502. A high-voltage signal is supplied to the column line of the selected memory cell, and 0 V is fed to the column lines of the other memory cells. In addition, the memory sense line 595 is at a high voltage, and the memory sense program line 577, 578 . . . 580 of the column line of the selected memory cell is at a high voltage by the circuits 541 through 544. The program circuits 519, 523 and the sense circuits 521, 525 are not activated in the erasing mode, and the data line 597 is at 0 V or in the floating state. The memory ground line 604 is grounded in the erasing mode. Thus, a high voltage (for example, 20 V) is applied to the gate of the memory cell of the selected column line, and the drain and source are grounded. At this time, the Fowler-Nordheim tunnel phenomenon occurs, causing electrons to be injected from the drain into the floating gate so that the threshold value of the memory cell transistor becomes high (for example, 5 through 8 V).
When the erased memory cell is rendered to the program state, the address data for program is supplied to the address input terminals 501, 502, 503, 505. In the program mode, the signal line 594 is supplied with a high voltage, the signal line 595 with 0 V, and the second high-voltage signal line 596 with a high voltage. The memory ground line 604 is rendered to the floating state. The column decoder 516, the row decoder 517, the program circuits 519, 523 and the data input buffers 520, 524 are activated, and the sense circuits 521, 525, and the data output buffers 522, 526 are deactivated. In other words, when a low voltage is supplied as input data to the input/output terminal 508, the program circuit 519 produces a high voltage (for example, 20 V) on the signal line 597, and when a high voltage is supplied to the input/output terminal 508, it produces 0 V on the signal line 597. When the signal line 597 is at a high voltage, a high-voltage signal is supplied to the selected one of the signal lines 585 through 588, and thus the selected row line is at a high voltage (for example, 20 V). The selected column line is also at a high voltage, and the memory sense program lines 577, 578 . . . 580 are at 0 V. Thus, the gate of the memory cell transistor is at 0 V, and the drain is at a high voltage (for example, 20 V). At this time, the Fowler-Nordheim tunneling is caused to discharge electrons from the floating gate to the drain, and inject holes from the drain into the floating gate, so that the threshold voltage of the memory cell transistor is reduced to, for example, -3 V to 0 V.
The circuit function of the conventional EEPROM has been described as above. The Fowler-Nordheim tunnel current on the storage principle is proportional to the electric field applied across the insulating film as expressed by the equation (1) in the document 2. The threshold value of the memory cell transistor is changed linearly with the high voltage in the erase or program mode as shown in FIGS. 6 and 9 in the document 2. In the conventional EEPROM, only a single high voltage value is used for each of the erase mode and program mode. Even in the read mode, only a binary value of a high or low value can be detected.